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Features
General
* Based on the ARM(R) SC100TM SecureCoreTM 32-bit RISC Processor * Two Instruction Sets * * * * * * * * *
- ARM High-performance 32-bit Instruction Set - Thumb(R) High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture - Single 32-bit Data Bus for Instructions and Data 3-stage Pipeline Architecture - Fetch, Decode, and Execute Stages 8-bit, 16-bit, and 32-bit Data Types On-chip Programmable System Clock up to 38MHz Very Low Power Consumption - Industry Leader in MIPS/Watt - Low power Idle and Power down Modes Bond Pad Locations Confirming to ISO7816-2 ESD Protection to 6000V Operating range: 1.62V to 5.5V Compliant with GSM, 3G , PC Industry Compatible, EMV
32-bit Secure Microcontrollers AT91SC464384RCU Summary
Memory
* 464K Bytes of ROM Program Memory * 384K Bytes of EEPROM, Including 256 OTP Bytes * * * *
- Typically More than 500,000 Write/Erase Cycles at a Temperature of 25C - 10 Years Data Retention EEPROM Erase Only Mode Write EEPROM With or Without Autoerase 18K Bytes of RAM (2K Bytes shared with AdvXTM crypto processor) 32K Bytes of ROM dedicated to Atmel's crypto Library
Peripherals
* One ISO 7816 Controller
- Up to 625 Kbps at 5 MHz Single Wire Interface (Digital Interface to RF front end chip) Two 16-bit Timers Random Number Generator (RNG) 2-level, 15-vector Interrupt Controller Hardware DES and Triple DES (DPA Resistant) Checksum Accelerator CRC16 & 32 Engine 32-bit Cryptographic Accelerator for Public Key Operations - RSA, DSA, ECC, Diffie-Hellman * High performance Hardware Java Card Accelerator
* * * * * * * *
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Note: This is a summary document. A complete document will be available under NDA. For more information, please contact your local Atmel sales office.
Security
* * * * *
Dedicated Hardware for Protection Against SPA/DPA Attacks Protection Against Physical Attack Environmental Protection Systems Voltage, Frequency, Light, and Temperature Protection Systems Secure Memory Management/Access Protection
Development Tools
* Hardware Development Support on the ATV4-91SC Voyager Emulation Platform * Software Libraries and Application Notes
Description
The AT91SC464384RCU is a low power, high performance, 32-bit RISC microcontroller with ROM program memory, EEPROM data memory, and cryptographic accelerator, based on the ARM SC100 advanced secure processor. This general purpose 32-bit processor offers high performance, very low power consumption, and additional features to help combat fraud. The AT91SC464384RCU features 384K bytes of high performance EEPROM (fast erase/write time, high endurance). On top of the SC100s MPU, a real hardware firewall can be used to increase the overall security level of the application without intense software development. The cryptographic accelerator featured in the AT91SC series is the AdvX., an N-bit multiplier-accumulator dedicated to performing fast encryption and authentication functions. AdvX is based on a custom 32-bit co-processor, thus enabling fast computation and low power operation. The AdvX in conjuction with controlling firmware running within the SC100 core, supports standard finite arithmetic functions (including RSA, DSA, DH and ECC) and GF(2N). Unique hardware features significantly accelerate the execution of Java Card Byte Code by removing the common software bottlenecks encountered during the implementation of a Java Virtual Machine. Additional security features include power and frequency protection logic, logical scrambling on program data and addresses, power analysis countermeasures, and memory access controlled by a supervisor mode.
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AT91SC464384RCU
Pin Configuration
The AT91SC512384RCT pinout configuration confirms to the ISO7816-2 interface. Note: By convention, the RST pin corresponds to the RST signal of the ISO7816-3 Protocol, both are active low.)
GND Vcc ISO I/O0 ISO CLK ISO RST C6 Ground (reference voltage) Power Supply Input Input or Output for serial data (ISO7816 Clock signal input to external clock operating circuit Reset signal input, a low state stops the ARM core SWP dedicated pin
Architectural Overview
The SC100 is a 3 stage pipeline, 32-bit RISC processor. It uses a Von Neumann Load/store architecture, this architecture is characterized by a single data and address bus for instruction data. The SC100 processor employs a unique architectural strategy known as Thumb(R), a super reduced instruction set that is ideally suited for high volume applications with memory restrictions, and applications where code density is an important factor. Essentially, the SC100 processor has two instruction sets: * The standard ARM instruction set using 32-bit instructions and offering maximum performance * The Thumb instruction set using 16-bit instructions and offering maximum code density Both instruction sets operate on 8-bit, 16-bit and 32-bit data types. The Thumb's 16-bit instruction length allows it to achieve almost twice the density of standard ARM code, whilst retaining most of the ARM performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because the 16-bit Thumb instructions operate on the same 32-bit register set as the 32-bit ARM instruction set. Thumb code can be up to 35% smaller than the equivalent ARM code, whilst providing 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system. Figure 1 shows the block diagram of the AT91SC464384RCU device.
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Figure 1. AT91SC464384RCU block diagram
8/16/32 OTP EEPROM Use Memory r ROM Program Memory 8/16/32 Jav a Acce lerator
AdvX Cry ptoAcce lerator
Sec ure Control
CLK GND VCC
RNG
Res et Circuit
RST
32
DES/3DES
CRC16&32 Engine
RAM
32
On-chip security (SPA, DPA, ...) I/O0 Firewall
SWP
C6
Timer
SC100TMore C
MPU 32 32 ISO 7816 Controller ISO 7816 I/O Por 0 t I/O0
Thumb Instruction decompressor 32 Pipeline
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